In order to perform a photolithographic process for forming a pattern when manufacturing a semiconductor device, various key patterns exist on a scribe line for performing align and overlay. FIG. 1 is a sectional view showing a key pattern formed in a semiconductor device according to a related art.
As shown in FIG. 1, a chemical mechanical polishing (CMP) process may be performed on an oxide layer 12 deposited over a semiconductor substrate 10, with a key pattern formed on a scribe line (S) defining cell areas (C). Since a removal rate of a sloped part (A) of the oxide layer 12 deposited on the key pattern is relatively high as compared with those of the cell areas, a discoloration phenomenon occurs. If the discoloration phenomenon on the scribe line (S) spreads to the cell area (C), a defocus phenomenon may be caused during subsequent processes for forming a via. As a result, a hole may not be defined, so the via may not be formed.